Figure 6

FPGA-based implementation of the IR module in CV-QKD systems. (a) Fully pipelined non-multiplexed structure for 5-level slice reconciliation. \(Decoder\_4\) and \(Decoder\_5\) modules are FPGA-based LDPC decoders in levels 4 and 5, respectively. \(LLR\_ini\_4\) and \(LLR\_ini\_5\) modules are used to generate the initial LLR of levels 4 and 5 before iterative decoding, respectively. \(Key\_Manager\) module is used to store the corrected secret keys and manage their inputs and outputs. From Ref. [55]. (b) Two-level multiplexing structures for 5-level slice reconciliation. \(Decoder\) module is multiplexed in two levels. (c) Diagram of the multidimensional reconciliation scheme. Here, d-dimensional random vector u is generated from a random binary sequence \((b_{1}, b_{2}, \ldots , b_{8})\). Random binary sequence \((b_{1}, b_{2}, \ldots , b_{16})\) and PCM H are multiplied to obtain the syndrome. From Ref. [110] with a minor modification. All figures are adapted with permission. (a) and (b) are adapted with permission from [55], ©2020 by IEEE. (c) is adapted with permission from [110], ©2022 by the authors