Table 1 Summary of implementation results for standard MSA decoder (‘Hard Syndrome’ decoder) architecture with 6-bit quantization (xcvu095 FPGA device, 20 nm CMOS process)
From: Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures
Code 〚n,k,d〛 | 〚442,68,10〛 | 〚544,80,12〛 | 〚714,100,16〛 | 〚1020,136,20〛 | 〚1428,630,24〛 |
Clock period | 8 ns | 8 ns | 8 ns | 8 ns | 10 ns |
Total latency (@30it) | 480 ns | 480 ns | 480 ns | 480 ns | 600 ns |
Lookup Table (LUT) | 69,586 (13%) | 85,487 (15.9%) | 16112,042 (20.8%) | 159,564 (29.7%) | 221,022 (41.1%) |
Flip Flop (FF) | 15,801 (1%) | 19,427 (1.8%) | 25,472 (2.4%) | 36,339 (3.4%) | 50,834 (4.7%) |
Power | 1.77 W | 2.7 W | 3.02 W | 4.43 W | 4.64 W |