Table 2 Summary of implementation results for the ‘Soft Syndrome’ decoder architectures with 8-bit quantization (xcvu095 FPGA device, 20 nm CMOS process)
From: Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures
Code 〚n,k,d〛 | 〚442,68,10〛 | 〚544,80,12〛 | 〚714,100,16〛 | 〚1020,136,20〛 | 〚1428,630,24〛 |
Clock period | 9.5 ns | 10 ns | 10 ns | 10 ns | 12 ns |
Total latency (@30it) | 570 ns | 600 ns | 600 ns | 600 ns | 720 ns |
Lookup Table (LUT) | 104,482 (19.4%) | 128,004 (23.8%) | 168,150 (31.3%) | 237,422 (44.2%) | 335,109 (62.3%) |
Flip Flop (FF) | 24,063 (2, 3%) | 30,257 (2.814%) | 39,684 (3.7%) | 48,657 (4.5%) | 79,267 (7.4%) |
Power | 1.67 W | 1.94 W | 2.39 W | 4.26 W | 4.59 W |