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Figure 3 | EPJ Quantum Technology

Figure 3

From: Methodology for bus layout for topological quantum error correcting codes

Figure 3

Figure reproduced with permission from Ref. [ 9 ]: quantum circuit for the plaquette reduction method. (a) Full circuit for the plaquette reduction method to calculate the value of the plaquette operator \(B_{p}\). The numbering of the qubits is that of Figure 2(b). The individual gates of the circuit are detailed in (b). (b) Each element of the circuit in (a) is reduced to X-gates, S-gates, single qubit rotations \(R(\rho \hat{y})\) by an angle ρ along the y-axis, controlled-X gates, controlled-S gates, and Toffoli gates.

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