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Figure 8 | EPJ Quantum Technology

Figure 8

From: Methodology for bus layout for topological quantum error correcting codes

Figure 8

Pictorial representation of the optimal scalable solution of Table  6 . The TLRs couple qubits inside unit cell 0 to the rest of the lattice. This architecture can be translated to cover the whole lattice without generating doubled TLRs. The TLRs are represented by solid and dashed lines for clarity when they traverse the same path. The squares denote the starting and ending points of TLRs. Note that the four qubit TLR, that contains qubits \(\alpha_{0,8}\), \(\alpha_{0,7}\), \(\alpha_{1,4}\), \(i_{0,1}\) has not be drawn, but instead we have drawn it translated (yellow, dashed) for the sake of a clear figure.

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