Figure 4

Explicit forms of the parallelized scheme for \({X}^{k}\) gates. The parallelized scheme, exemplified for \(d = n = 8\) and \(1 \le k \le d/2\), consists of a path permutation sandwiched between two swaps. The swap operator comprises a network of OAM exchangers, whose structure is depicted in Fig. 1, and a series of H blocks (in the present case there are two such blocks per one swap). The presented schemes can be simplified by removing the exchangers that do not affect the final state. These are drawn in faded colors and enclosed in dashed boxes. The input paths of the swap operator should be permuted to comply with formula (13). As this path permutation does not affect our discussion, we omit it in the figure for clarity. (a) Parallelized X gate. (b) Parallelized \({X}^{2}\) gate. (c) Parallelized \({X}^{3}\) gate. (d) Parallelized \({X}^{4}\) gate