Designs of the divider and special multiplier optimizing T and CNOT gates

Abstract

Quantum circuits for multiplication and division are necessary for scientific computing on quantum computers. Clifford + T circuits are widely used in fault-tolerant realizations. T gates are more expensive than other gates in Clifford + T circuits. But neglecting the cost of CNOT gates may lead to a significant underestimation. Moreover, the small number of qubits available in existing quantum devices is another constraint on quantum circuits. As a result, reducing T-count, T-depth, CNOT-count, CNOT-depth, and circuit width has become the important optimization goal. We use 3-bit Hermitian gates to design basic arithmetic operations. Then, we present a special multiplier and a divider using basic arithmetic operations, where ‘special’ means that one of the two operands of multiplication is non-zero. Next, we use new rules to optimize the Clifford + T circuits of the special multiplier and divider in terms of T-count, T-depth, CNOT-count, CNOT-depth, and circuit width. Comparative analysis shows that the proposed multiplier and divider have lower T-count, T-depth, CNOT-count, and CNOT-depth than the current works. For instance, the proposed 32-bit divider achieves improvement ratios of 40.41 percent, 31.64 percent, 45.27 percent, and 65.93 percent in terms of T-count, T-depth, CNOT-count, and CNOT-depth compared to the best current work. Further, the circuit widths of the proposed n-bit multiplier and divider are 3n. I.e., our multiplier and divider reach the minimum width of multipliers and dividers, keeping an operand unchanged.

1 Introduction

One of the most significant challenges in quantum computing is the realization of quantum computers [1]. The quantum circuit model is a realistic quantum computer model [2] and promotes the efficient implementation of quantum algorithms such as quantum image processing [3, 4], quantum transforms [5, 6], and quantum amplitude estimation [7].

Quantum circuits for arithmetic operations as the vital part of a quantum computer’s reversible arithmetic logic unit can be realized by quantum gates [8, 9]. For instance, Noorallahzadeh et al. used elementary quantum gates in the NCV (NOT, CNOT, Controlled-V, and Controlled-V+) library to design quantum multipliers [10–12]. These multipliers have the low quantum cost, garbage output, and constant input. The fault-tolerant implementation of quantum gates is needed for robust quantum computing in the presence of noise. Clifford + T circuits are widely accepted solutions to fault-tolerant implementation [13, 14]. An instruction set $\{ H,S,{S^{\dagger }},CNOT,T,{T^{\dagger }}\}$ can be used to implement quantum gates [15].

The T gates are more expensive than other gates in terms of space and time cost due to their increased tolerance to noise errors [16, 17]. Since the CNOT gate is the only double-qubit gate in the Clifford + T gate set, neglecting the cost of the CNOT gates may lead to a significant underestimation [18, 19]. Therefore, the number of T gates (T-count), the maximum number of T gates in any circuit path (T-depth), CNOT-count, and CNOT-depth are the main performance indicators of Clifford + T circuits.

Toffoli, Fredkin, Peres, and TR gates are typical for the design of quantum arithmetic operations [20–22]. Clifford + T circuits with T-depth 3 and T-count 7 for Toffoli, Fredkin, Peres, and TR gates have been proposed without ancillae [17, 18, 23]. Their CNOT-counts are 7, 9, 6, and 6, respectively. Compared with Peres and TR gates, the Hermitian Toffoli gate has a better symmetry performance. Four 3-bit Hermitian gates were presented in [24], whose T-depth, T-count, and CNOT-count are 3, 7, and 6. Therefore, these Hermitian gates in [24] have better symmetry than Peres or TR gates and the smaller CNOT-count than the Toffoli gate. So, we use these Hermitian gates to design the divider and special multiplier in this paper.

In the past decade, quantum circuit designs for arithmetic operators, including adders, modular adders, and comparators, were actively studied [23, 25–33]. Some arithmetic operations have $O(\log n)$ T-depth but require lots of ancillae. For example, an n-bit adder with the minimal T-count $4n-4$ was proposed in [30]. But the adder needs $2n-2$ measurements and $n-1$ ancillae. In addition, arithmetic operators with the minimum circuit width (0 ancillae) were designed in [23, 32].

Thapliyal et al. used ancillae to realize n-bit multipliers with two unchanged operands, so their circuit width is $4n+1$ [34, 35]. To reduce the T-count and circuit width, Li et al. utilized Peres and TR gates to design the multiplier with two unchanged operands and the circuit width 4n [23]. Two multipliers with an unchanged operand and the circuit width $3n+1$ were implemented using approximate Toffoli, Peres, and TR gates [36]. They have smaller T-counts, T-depths, and circuit widths than other multipliers proposed in [23, 34, 35]. A quantum divider based on quantum Fourier transform was designed with the circuit width 4n [37]. Thapliyal et al. replaced Toffoli gates with the complex quantum Fourier transform to realize two divisions with fewer qubits [38]. The two dividers have circuit widths $3n+3$ and $3n+2$. To further reduce circuit width, Li et al. designed a divider with the circuit width 3n [36]. The above multipliers and dividers do not consider optimizing CNOT-count and CNOT-depth.

Quantum algorithms may likely be implemented in these noisy intermediate-scale quantum (NISQ) devices [39]. Some algorithms, such as a quantum convolutional neural network, have been proposed for NISQ devices [40, 41]. The large circuit width blocks applications of algorithms in NISQ devices, so the small circuit width is crucial for algorithms applied in NISQ devices. Since an n-bit divider with an unchanged operand needs at least 3n qubits to store the n-bit operand and 2n-bit result, we will use 3n qubits to realize a multiplier and a divider, respectively. In this paper, we design some basic arithmetic operations such as the modular adder and controlled modular adder. Then, we propose a special multiplier where ‘special’ means that one of the two operands of multiplication is not equal to zero, such as the multiplication $s=a\times b$ with $a\neq 0$. Since the division $s/a$ is the inverse operation of the special multiplication $s=a\times b$, we can obtain a divider circuit modifying the proposed special multiplier. Finally, the optimized Clifford + T circuits of the divider and special multiplier are presented.

The rest of this paper is organized as follows. In Sect. 2, we review the background knowledge. Section 3 presents basic arithmetic operations. In Sects. 4 and 5, we propose the special multiplier and divider. Comparative analysis and conclusions are drawn in Sects. 6 and 7.

2 Background

For clarity, we briefly introduce 3-bit Hermitian gates in [24] and approximate Toffoli gates in [36]. The matrix forms of six Clifford + T gates are defined by

$$\begin{aligned} &H = \frac{1}{{\sqrt {2} }}\begin{bmatrix} 1&1 \\ 1&{ - 1} \end{bmatrix},\qquad X = \begin{bmatrix} 0&1 \\ 1&0 \end{bmatrix},\qquad S = \begin{bmatrix} 1&0 \\ 0&i \end{bmatrix}, \\ &{S^{\dagger }} = \begin{bmatrix} 1&0 \\ 0&{ - i} \end{bmatrix} ,\qquad T = \begin{bmatrix} 1&0 \\ 0&{{e^{i\pi /4}}} \end{bmatrix},\qquad {T^{\dagger }} = \begin{bmatrix} 1&0 \\ 0&{{e^{ - i\pi /4}}} \end{bmatrix}. \end{aligned}$$

We use the instruction set $\{ H,X,S,{S^{\dagger }},CNOT,T,{T^{\dagger }}\}$ to realize the Clifford + T circuits for arithmetic operations in this paper. For instance, the implementations for the Toffoli, Fredkin, Peres, and TR gates are illustrated in Fig. 1 [15, 36].

Figure 1

Implementation circuits for (a) the Toffoli gate, (b) the Fredkin gate, (c) the Peres gate, and (d) an inverse-Peres gate named TR. Note: The circuit of the Toffoli gate has an error in [36], so we have modified the error in the dashed box 1 in (a)

Figure 1 reveals that Peres and TR gates consist of a Toffoli gate and a CNOT gate, respectively. Similarly, four Hermitian gates are constructed with Toffoli and CNOT gates [24]. The four Hermitian gates are denoted as LI1, LI2, LI3, and LI4 with ${\mathrm{{LI = \{ LI1,LI2,LI3,LI4\} }}}$. Their Clifford + T circuits are presented in Fig. 2.

Figure 2

Clifford + T circuits for (a) the LI1 gate, (b) the LI2 gate, (c) the LI3 gate, (d) the LI4 gate, and (e) the variant of the LI2 gate

Figure 2 reveals that LI1 and LI2 gates are essentially the same. Since we swap the lines of operands A and B, we can get LI from LI2 swaping the lines of operands A and B. Similarly, we obtain the gate in Fig. 2(e) by swapping the lines of operands C and B for the LI2 gate.

The optimization rule for two LI2 gates is illustrated in Fig. 3.

Figure 3

Rule 1 of two LI gates proposed in [36]. U is the combination of LI and Clifford gates

The implementations for the Toffoli and approximate Toffoli gates are shown in Fig. 4. Compared to the corresponding Toffoli gate in Fig. 4(a), the approximate Toffoli gate in Fig. 4(b) differs in that it maps $\vert {111} \rangle$ to $- \vert {111} \rangle$ [36]. In addition, we give Clifford + T circuits for two variants of the approximating Toffoli gate in Fig. 4(c) and (d).

Figure 4

Clifford + T circuits for (a) the Toffoli gate, (b) the approximate Toffoli gate, and the variants of the approximate Toffoli gate in (c) and (d)

3 Designs of basic arithmetic operations

This section gives Clifford + T circuits for some basic arithmetic operations, including the modular adder (MA), modular subtractor (MS), modular adder-subtractor (MAS), modular subtractor-adder (MSA), controlled modular adder (CMA), controlled modular subtractor (CMS), special modular adder (SMA), special modular subtractor (SMS), special modular adder-subtractor (SMAS), and special modular subtractor-adder (SMSA). MS, MSA, CMS, SMS, and SMSA are inverses of MA, MAS, CMA, SMA, and SMAS, respectively.

3.1 Quantum circuits of basic arithmetic operations

We substitute LI2 gates for Peres and TR gates to realize the modular adder and subtractor in [23]. Their circuits presented in Fig. 5 implement the following n-bit operations:

$$ \textstyle\begin{cases} {| s \rangle = | {(a + b){\kern 1pt} \bmod { \kern 1pt} {2^{n}}} \rangle,} \\ {| d \rangle = | {(b - a){\kern 1pt} \bmod { \kern 1pt} {2^{n}}} \rangle,} \end{cases} $$

(1)

with $\vert b \rangle = \vert {{b_{n - 1}}{b_{n - 2}} \ldots {b_{0}}} \rangle$, $\vert a \rangle = \vert {{a_{n - 1}}{a_{n - 2}} \ldots {a_{0}}} \rangle$, $\vert s \rangle = \vert {{s_{n - 1}} \ldots {s_{0}}} \rangle$, $\vert d \rangle = \vert {{d_{n - 1}} \ldots {d_{0}}} \rangle$, ${b_{k}},{a_{k}}, {s_{k}}, {d_{k}} \in \{ 0,1\}$, and $k \in \{ 0,1, \ldots,{n-1}\}$.

Figure 5

Quantum circuits for (a) the modular adder (MA) and (b) the modular subtractor (MS)

Compared to MA, MS consists of the same gates with the inverted order. It reveals that the inverse of basic arithmetic operations based on LI gates can be realized by inverting the circuit order of the corresponding arithmetic operations. We use LI2 gates to design quantum circuits for the modular adder-subtractor (MAS) and the controlled modular adder (CMA) in Fig. 6, which implement

$$ \textstyle\begin{cases} h = (b + {( - 1)^{e}}a) \bmod {2^{n}}, \\ t = (b + \overline{e} a) \bmod {2^{n}}, \end{cases} $$

(2)

with $\vert h \rangle = \vert {{h_{n - 1}} \ldots {h_{0}}} \rangle$, $\vert t \rangle = \vert {{t_{n - 1}} \ldots {t_{0}}} \rangle$, ${h_{k}},{t_{k}}, e \in \{ 0,1\}$, and $k \in \{ 0,1, \ldots,{n-1}\}$.

Figure 6

Quantum circuits for (a) the modular adder-subtractor (MAS) and (b) the controlled modular adder (CMA). Due to ${X^{n}} = I$ for the even number n and ${X^{n}} = X$ for the odd number n, the circuit in box 1 consists of $\lceil {n/2} \rceil + 1$ CONT gates, where $\lceil . \rceil$ is a round-up symbol

When ${a_{n - 1}}{a_{n - 2}} \ldots {a_{1}}{a_{0}}$ is equal to $0{a_{n - 2}} \ldots {a_{1}}{a_{0}}$ for MA and MAS in Fig. 5 and Fig. 6, we can omit the most significant bit of $0{a_{n - 2}} \ldots {a_{1}}{a_{0}}$ and design the special modular adder (SMA) and special modular adder-subtractor (SMAS) to reduce circuit width. For instance, SMA can realize $\vert {({b_{n - 1}}{b_{n - 2}} \ldots {b_{0}} + {a_{n - 2}} \ldots {a_{0}}) \bmod {\kern 1pt} {2^{n}}} \rangle$ with $2n-1$ qubits. Their 4-bit examples are proposed in Fig. 7.

Figure 7

Quantum circuits for (a) the special modular adder (SMA) and (b) the special modular adder-subtractor (SMAS)

Compared to basic arithmetic operations based on Peres and TR gates in [23], the above arithmetic operations have an advantage: these arithmetic operations and their inverse can be realized using the same gates. Compared to basic arithmetic operations based on Toffoli gates in [32, 36, 38], the above arithmetic operations have fewer CNOT-count. For instance, the n-bit CMA in Fig. 6(b) can reduce approximately 2.5n CONT gates compared with the controlled modular adders based on Toffoli gates.

3.2 Optimized Clifford + T circuits for basic arithmetic operations

We present four rules for LI gates in Fig. 8 to optimize Clifford + T circuits. T-count, T-depth, CNOT-count, and CNOT-depth are selected as optimization goals. Rule 2 is given in Fig. 8(a) to optimize CNOT gates. Rules 3 and 4 are obtained by modifying rule 1 in Fig. 3. Rule 5 shows that the Clifford + T circuit in box 2 is for the circuit in box 1. Furthermore, for each iteration of the circuit in box 2, the gate in the box will be multiplied by ${T^{\dagger }}$. Therefore, the gate in box 3 becomes ${({T^{\dagger }})^{n}}$ after $n+2$ times iterate the circuit in box 2. We obtain ${({T^{\dagger }})^{n}} \in \{ {T^{\dagger }},{S^{\dagger }},{S^{\dagger }}{T^{ \dagger }},Z,Z{T^{\dagger }},Z{S^{\dagger }},T,I\}$ for any integer n using ${({T^{\dagger }})^{2}} = {S^{\dagger }}$, ${({T^{\dagger }})^{3}} = {S^{\dagger }}{T^{\dagger }}$, ${({T^{\dagger }})^{4}} = Z$, ${({T^{\dagger }})^{5}} = Z{T^{\dagger }}$, ${({T^{\dagger }})^{6}} = Z{S^{\dagger }}$, ${({T^{\dagger }})^{7}} = T$, and ${({T^{\dagger }})^{8}} = I$, where the matrix forms of the Clifford gates I and Z are $I=\left[\begin{array}{cc}1& 0\\ 0& 1\end{array}\right],Z=\left[\begin{array}{cc}1& 0\\ 0& -1\end{array}\right]$.

Figure 8

Three rules for LI gates including (a) rule 2, (b) rule 3, (c) rule 4, and (d) rule 5

We can use rules 3, 4, and 5 to optimize Clifford + T circuits for basic arithmetic operations. For instance, the optimized Clifford + T circuits for the 4-bit SMA,4-bit SMSA, and 3-bit CMA are presented in Fig. 9 and Fig. 10.

Figure 9

Optimized Clifford + T circuits for the 4-bit SMA and SMSA

Figure 10

The 3-bit CMA and its optimized Clifford + T circuit

Circuits in dashed boxes are iterative circuits of SMA, SMSA, and CMA. Increasing by 1-bit for SMA will increase 8 T-counts, 2 T-depths, 13 CNOT-counts, and 6 CNOT-depths. Therefore, the n-bit SMA has $8(n - 3) + 8 + 7 = 8n - 9$ T-counts, $2(n - 3) + 5 = 2n-1$ T-depth, $13(n - 3) + 17 = 13n-22$ CNOT-counts, and $6(n - 3) + 10 = 6n-8$ CNOT-depths. Similarly, we can calculate performance indexes for other basic arithmetic operations listed in Table 1.

Table 1 Performance indexes for n-bit basic arithmetic operations. HS-count denotes the total number of H and S gates

4 The design of the special multiplier

In this section, we design a special multiplier using LI and approximate Toffoli gates.

4.1 The circuit for the special multiplier optimizing CNOT gates

The special multiplication $s=ab$ can be expressed by

$$ s = ba = \sum_{k = 0}^{n - 1} {{b_{k}} {2^{k}}a} $$

(3)

with $\vert b \rangle = \vert {{b_{n - 1}}{b_{n - 2}} \ldots {b_{0}}} \rangle$, $\vert a \rangle = \vert {0{a_{n - 1}}{a_{n - 2}} \ldots {a_{0}}} \rangle$, and $a \ne 0$.

Since $a + b = (a + b)\bmod {2^{n + 1}}$ holds for any two n-bit positive integers, an n-bit addition can be realized by $(n+1)$-bit modular adders. It is the reason that the n-bit integer a in (3) is expressed as ${0{a_{n - 1}}{a_{n - 2}} \ldots {a_{0}}}$.

Equation (3) is rewritten as

$$ s = - \overline {{b_{0}}} a - \sum _{k = 1}^{n - 1} {{{( - 1)}^{{b_{k}}}} {2^{k - 1}}a} + {2^{n - 1}}a $$

(4)

with $\vert b \rangle = \vert {{b_{n - 1}}{b_{n - 2}} \ldots {b_{0}}} \rangle$, $\vert a \rangle = \vert {0{a_{n - 1}}{a_{n - 2}} \ldots {a_{0}}} \rangle$, $\overline {{b_{0}}} = 1 - {b_{0}}$, and $a \ne 0$.

Special arithmetic operations in Fig. 7 and their inverses can be adopted for the operand ${0{a_{n - 1}}{a_{n - 2}} \ldots {a_{0}}}$. I.e., we can omit the most significant bit of ${0{a_{n - 1}}{a_{n - 2}} \ldots {a_{0}}}$ using special arithmetic operations. Thus, we can use a CMS, $(n-1)$ SMSA, and an SMA to realize the special multiplication in (4). The circuits for the 2-bit and 3-bit special multipliers are shown in Fig. 11. Swap gates between basic arithmetic operations are used to shift quantum lines. The output $\vert {{s_{5}}{s_{4}}{s_{3}}{s_{2}}{s_{1}}{s_{0}}} \rangle$ equals to $\vert {ba} \rangle$.

Figure 11

The circuits for (a) a 2-bit special multiplier and (b) a 3-bit special multiplier. The outputs $\vert {{s_{3}}{s_{2}}{s_{1}}{s_{0}}} \rangle$ and $\vert {{s_{5}}{s_{4}}{s_{3}}{s_{2}}{s_{1}}{s_{0}}} \rangle$ equal to $\vert {ba} \rangle$, respectively

The CMS in Fig. 11 perfects the operation $(0 - {\bar{b}_{0}}a)\bmod {2^{n}}$, which can be rewritten by

$$ (0 - {\bar{b}_{0}}a)\bmod {2^{n}} = ({b_{0}}a - a)\bmod {2^{n}}, $$

(5)

with $a = {a_{n - 1}} \ldots {a_{1}}{a_{0}}$ and ${a_{n - 1}}, \ldots,{a_{1}},{a_{0}},{b_{0}} \in \{ 0,1\}$. The circuits for the operation $(0 - {\bar{b}_{0}}a)\bmod {2^{n}}$ with $n =2,3$ are presented in Fig. 12. We replace CMS in the first column with circuits in the second column to realize (5). Since the LI2 gate changes $\vert {{a_{1}}} \rangle \vert 0 \rangle \vert {{a_{0}}} \rangle$ into $\vert {{a_{1}} \oplus {a_{0}}} \rangle \vert 0 \rangle \vert {{a_{0}}} \rangle$, we substitute CNOT gates for LI2 gates to obtain circuits in the third column. Finally, we give circuits based on LI and approximate Toffoli gates in the fourth column. The circuit for $(0 - {\bar{b}_{0}}a)\bmod {2^{n}}$ is presented in Fig. 13.

Figure 12

The circuits for the operation $(0 - {\bar{b}_{0}}a)\bmod {2^{n}}$ with (a) $n =2$ and (b) $n=3$

Figure 13

The n-bit circuit for the operation in (5). $\vert {{t_{n - 1}} \ldots {t_{1}}{t_{0}}} \rangle$ equals to $\vert {({b_{0}}a - a)\bmod {2^{n}}} \rangle$

We give circuits in the left in Fig. 14(b) and the top in Fig. 14(c) by shifting lines directly to replace Swap gates (see Fig. 14(a)), substituting circuits in Fig. 12 for CMS and eliminating some CNOT gates. Then, we obtain the circuits optimizing CNOT gates in Fig. 14 for the 2-bit and 3-bit special multipliers using rule 3.

Figure 14

The circuits optimizing CNOT gates for (a) shifting quantum lines to replace the Swap gate, (b) the 2-bit special multiplier and (c) the 3-bit special multiplier. Rule 3 shows that circuits in dashed boxes are equivalent to LI4 gates

For clarity, we give the circuit for the 4-bit special multiplier in Fig. 15(a). The circuits in the dashed boxes 1, 2, and 3 are named the first module of the multiplier (FMM), the iterative module of the multiplier (IMM), and the last module of the multiplier (LMM), respectively. Next, we use these modules to design the n-bit special multiplier in Fig. 15(b).

Figure 15

The circuits optimizing CNOT gates for (a) the 4-bit special multiplier and (b) the n-bit special multiplier

4.2 Clifford + T circuits for the special multiplier

We give the Clifford + T circuit for the 2-bit special multiplier in Fig. 16 using rules 3 and 4. The circuit in dashed box 1 is provided using the Clifford + T circuit for the approximate Toffoli gate in Fig. 4(b). The circuit in dashed box 2 is another implementation based on Clifford + T gates for the LI4 gate.

Figure 16

The Clifford + T circuit for the 2-bit special multiplier

Using rule 4, we present the Clifford + T circuit of FMM for the 4-bit special multiplier in Fig. 17. The iterative circuit of FMM is given in the dashed box. Figure 17 reveals that increasing by 1-bit for FMM increases 18 T-counts, 4 T-depths, 21 CNOT-count, and 9 CNOT-depth. Therefore, we obtain performance indexes of the FMM for the n-bit special multiplier by calculating

$$ \textstyle\begin{cases} {\text{FMM's T-count: }} 18(n - 2) + 23 = 18n - 13, \\ {\text{FMM's T-depth: }} 4(n - 2) + 10 = 4n + 2, \\ {\text{FMM's CNOT-count: }} 21(n - 2) + 27 = 21n - 15, \\ {\text{FMM's CNOT-depth: }} 9(n - 2) + 16 = 9n - 2. \end{cases} $$

(6)

Figure 17

The Clifford + T circuit of FMM for the 4-bit special multiplier

We propose Clifford + T circuits of the IMM and LMM for the 4-bit special multiplier in Fig. 18 using rules 3 and 4. Analyzing iterative circuits in dashed boxes, we calculate the performance indexes of the IMM and LMM as follows:

$$ \textstyle\begin{cases} {\text{IMM's T-count: }} 8(n - 2) + 15 = 8n - 1, \\ {\text{IMM's T-depth: }} 2(n - 2) + 5 = 2n +1, \\ {\text{IMM's CNOT-count: }} 11(n - 2) + 19 = 11n - 3, \\ {\text{IMM's CNOT-depth: }} 4(n - 2) + 12 = 4n +4, \end{cases} $$

(7)

and

$$ \textstyle\begin{cases} {\text{LMM's T-count: }} 8(n - 2) + 15 = 8n - 1, \\ {\text{LMM's T-depth: }} 2(n - 2) + 5 = 2n +1, \\ {\text{LMM's CNOT-count: }} 13(n - 2) + 19 = 13n - 7, \\ {\text{LMM's CNOT-depth: }} 5(n - 2) + 12 = 5n +2. \end{cases} $$

(8)

Figure 18

Clifford + T circuits of IMM and LMM for the 4-bit special multiplier including (a) IMM and (b) LMM

For clarity, we give performance indexes of the 2-bit special multiplier, n-bit special multiplier ($n \ge 3$), and its modules in Table 2.

Table 2 Performance indexes the special multiplier and its modules with $n \ge 3$

5 The design of the divider

In this section, we design a divider using LI and approximate Toffoli gates.

5.1 The circuit for the divider optimizing CNOT gates

The division $s/a$ is the inverse operation of the special multiplication $s=ba$ with $a \ne 0$. We obtain a divider by reversing the circuit order for the special multiplier in Fig. 11. Therefore, we can use an SMS, $(n-1)$ SMAS, and a CMA to realize the divider. For instance, the 2-bit and 3-bit dividers are presented in Fig. 19.

Figure 19

The circuits for (a) a 2-bit divider and (b) a 3-bit divider. The outputs $\vert {{q_{1}}{q_{0}}} \rangle$ and $\vert {{q_{2}}{q_{1}}{q_{0}}} \rangle$ are quotients of the division $\vert {s/a} \rangle$; $\vert {{r_{1}}{r_{0}}} \rangle$ and $\vert {{r_{2}}{r_{1}}{r_{0}}} \rangle$ are remainders of the division $\vert {s/a} \rangle$

The SMS in Fig. 19 perfects the following operation:

$$ ({s_{n - 2}} - a) \bmod {2^{n}}, $$

(9)

with $a = {a_{n - 2}} \ldots {a_{1}}{a_{0}}$ and ${a_{n - 2}}, \ldots,{a_{1}},{a_{0}},{s_{n-2}} \in \{ 0,1\}$.

We design circuits in Fig. 20 for the special operation in (9) using approximate Toffoli gates in Fig. 4(c) and (d).

Figure 20

The circuits realizing the special operation in (9) including (a) $n = 3$, (b) $n = 4$, and (c) $n \ge 4$

Firstly, we substitute circuits in Fig. 20 for SMS and eliminate some CNOT gates. Then, we use rule 2 to design circuits of the 2-bit and 3-bit dividers optimizing CNOT gates in Fig. 21(a) and (b). Circuits in dashed boxes in Fig. 21(b) are named the first module of the divider (FMD), the iterative module of the divider (IMD), and the last module of the divider (LMD), respectively. Finally, we use the three modules to design the n-bit divider in Fig. 21(c).

Figure 21

The circuits optimizing CNOT gates for (a) the 2-bit divider, (b) the 3-bit divider, and (c) the n-bit divider ($n \ge 3$)

5.2 Clifford + T circuits for the divider

We use rule 5 and Clifford + T circuits for approximate Toffoli gates in Fig. 4 to design the Clifford + T circuit of the 2-bit divider in Fig. 22. Clifford + T circuits in dashed boxes 1 and 2 in Fig. 22 correspond to circuits in dashed boxes 1 and 2 in Fig. 21(a).

Figure 22

The Clifford + T circuit for the 2-bit divider

Similarly, we propose the Clifford + T circuit for the FMD in Fig. 23(a) using approximate Toffoli gates in Fig. 4. The Clifford + T circuit for the IMD is presented in Fig. 23(b) using rule 5.

Figure 23

Clifford + T circuits for (a) the FMD and (b) the IMD. Circuits in dashed boxes are iterative circuits of the FMD and IMD, respectively

We calculate performance indexes of the FMD and LMD by analyzing iterative circuits in dashed boxes in Fig. 23:

$$ \textstyle\begin{cases} {\text{FMD's T-count: }} 4(n - 2) + 8 = 4n, \\ {\text{FMD's T-depth: }} (n - 2) + 3 = n +1, \\ {\text{FMD's CNOT-count: }} 7(n - 2) + 12 = 7n - 2, \\ {\text{FMD's CNOT-depth: }} 3(n - 2) + 8 = 3n +2, \end{cases} $$

(10)

and

$$ \textstyle\begin{cases} {\text{IMD's T-count: }} 8(n - 2) + 15 = 8n - 1, \\ {\text{IMD's T-depth: }} 2(n - 2) + 5 = 2n +1, \\ {\text{IMD's CNOT-count: }} 11(n - 2) + 19 = 11n - 3, \\ {\text{IMD's CNOT-depth: }} 4(n - 2) + 12 = 4n +4. \end{cases} $$

(11)

The Clifford + T circuit for the LMD is presented in Fig. 24 using rule 5. From Fig. 24, we give performance indexes of the LMD as follows:

$$ \textstyle\begin{cases} {\text{LMD's T-count: }} \le 20(n - 2) + 32 = 20n - 8, \\ {\text{LMD's T-depth: }} 5(n - 2) + 10 = 5n, \\ {\text{LMD's CNOT-count: }} 26(n - 2) + 38 = 26n - 14, \\ {\text{LMD's CNOT-depth: }} 14(n - 2) + 24 = 14n -4. \end{cases} $$

(12)

Figure 24

The Clifford + T circuit for the LMD. The circuit in dashed box 2 is the iterative circuit of the LMD. For each iteration of the circuit in box 2, the gate in dashed box 1 will be multiplied by ${T^{\dagger }}$

Furthermore, we give performance indexes of the 2-bit divider, n-bit divider ($n \ge 3$), and its modules in Table 3.

Table 3 Performance indexes the divider and its modules with $n \ge 3$

6 Comparative analysis

6.1 Comparisons of basic arithmetic operators

The section Introduction shows that the adder has the best T-count $4n-4$ in [30]. But the adder needs $2n-2$ measurements. It is thus not directly comparable with the T-count. Considering the circuit width, T-count, T-depth, CNOT-count, and CNOT-depth, we compare the proposed works with the rest basic arithmetic operators in [23, 29, 33, 36, 38]. The results are presented in Table 4. Table 4 shows that the proposed basic arithmetic operators are superior to the others.

Table 4 Comparisons of basic arithmetic operators

Objectively, compared with these operators in [36], the proposed basic arithmetic operations have only a slight advantage regarding performance indexes. However, the proposed basic arithmetic operators have a significant advantage: They are more convenient for designs of the multiplier and divider. For instance, the proposed controlled modular adder can be used to realize the LMD of the divider with excellent performance indexes (see Fig. 24).

Note: Thapliyal et al. use the adder and subtractor in [32, 33] to an efficient divider in [38]. We calculate the performance indexes of the divider in [38] because it is one of the main comparison objects of the divider proposed in this paper. Therefore, we describe the computation process of the adder and subtractor in [32, 33] as follows. Circuits of the 4-bit adder and subtractor are shown in Fig. 25. The n-bit adder in Fig. 25(a) is modified to the n-bit subtractor in Fig. 25(b) by adding $3n+1$ X gates. They consist of $4n-5$ CNOT, $n-1$ Toffoli, and n Peres gates, respectively. The adder and subtractor can be modified into the modular adder and subtractor by eliminating the high bit (see Fig. 25(c) and (d)). The generated modular subtractor named Subtraction in [38] comprises $4n-5$ CNOT gates, $n-1$ Toffoli gates, and $n-1$ Peres gates. Furthermore, Thapliyal develops a reversible adder-subtractor in [33] by adding $3n+1$ CNOT gates to the n-bit adder in Fig. 25(a). Similarly, a modular adder-subtractor is obtained by eliminating the high bit of the reversible adder-subtractor in [33]. Therefore, the n-bit modular adder-subtractor named Ctrl-AddSub in [38] consists of $7n-5$ CNOT, $n-1$ Toffoli, and $n-1$ Peres gates. Clifford + T circuits of Toffoli gates proposed in [15, 23, 36] have T-count 7, T-depth 3, CNOT-count 7, and CNOT-depth 6. The Clifford + T circuit of the Peres gate with T-count 7, T-depth 3, CNOT-count 6, and CNOT-depth 5 is proposed in [23]. The performance indexes of Subtraction are given by

$$ \textstyle\begin{cases} {\text{T-count: }} 7(n-1)+7(n-1)= 14n-14, \\ {\text{T-depth: }} 3(n-1)+ 3(n-1) = 6n-6, \\ {\text{CNOT-count: }} 4n-5+7(n-1)+6(n-1)= 17n-18, \\ {\text{CNOT-depth: }} 2n-1 + 6(n-1)+5(n-1)= 13n-12. \end{cases} $$

(13)

Similarly, the modular adder-subtractor (Ctrl-AddSub) has $14n-14$ T-counts, $6n-6$ T-depths, $17n-18+3n=20n-18$ CNOT-counts, and $13n-12+2=13n-10$ CNOT-depths.

Figure 25

The reversible 4-bit adder, subtractor, modular adder, and modular subtractor for (a) the adder in [32], (b) the subtractor in [33], (c) the modular adder, and the modular subtractor

6.2 Comparisons of multipliers and dividers

6.2.1 Method comparisons with previous works

The main contributions of this paper are to design the new multiplier and divider. Therefore, we provide a description of the new contributions in this section. Compared to multipliers based on the measure-and-fixup approach [42, 43], our method for the multiplier differs in that it does not require quantum measurements. Method comparisons with previous works [23, 35, 36] are presented in Table 5. Realization formulas of multipliers are

$$\begin{aligned} & {{\mathrm{{s = }}} - \overline {{b_{0}}} a - \sum _{k = 1}^{n - 1} {{{( - 1)}^{{b_{k}}}} {2^{k - 1}}a} + {2^{n - 1}}a}, \end{aligned}$$

(14)

$$\begin{aligned} & s = \sum_{k = 0}^{n - 1} {{b_{k}} {2^{k - 1}}a}, \end{aligned}$$

(15)

and

$$ {s = \bigl[ - \overline {{b_{0}}} + {{( - 1)}^{\overline {{b_{1}}} }}\bigr]a + {2^{n - 1}}a + \sum _{k = 2}^{n - 1} {{{( - 1)}^{ \overline {{b_{k}}} }} {2^{k - 1}}a} }, $$

(16)

where ${{b_{k}}}$ is equal to $1 - {b_{k}}$ with $k \in \{ 1,2, \ldots,n - 1\}$.

Table 5 Method comparisons of multipliers with previous works. RF, UO, OO, and OR denote realization formulas, unchanged operands, optimization objects, and optimization rules

Table 5 shows that the proposed method is different from methods in [23, 35] in terms of realization formulas, unchanged operands, and optimization objects. From realization formulas in Table 5, we obtain that methods in [23, 35] use n controlled modular adders to implement multipliers, respectively. Our method adopts the circuit in Fig. 13, $(n-1)$ special modular subtractor-adders, and a special modular adder to implement the multiplier. Compared to the method in [36], our method used the different realization formula, optimization objects, optimization rules, and realization of ${ - \overline {{b_{0}}} a}$. According to the realization formula in [36], the multiplier is implemented by a circuit named SM, $(n-1)$ modular adder-subtractors, and a modular adder, where the SM consists of a controlled modular subtractor and other gates to realize $[ - \overline {{b_{0}}} + {( - 1)^{\overline {{b_{1}}} }}]a$. The proposed multiplier reduces the circuit width, T-count, T-depth, CNOT-count and CNOT-depth, because the method in the paper uses the different realization formula, optimization objects, and optimization rules.

Due to the Hermitian property of LI gates, we can reverse the circuit order for the special multiplier to obtain the divider. The method for the divider in the paper is significantly different from methods of dividers in [36, 38].

6.2.2 Performance comparisons of multipliers

Multipliers based on the measure-and-fixup approach have small T-counts. For instance, T-counts of two multipliers in [42, 43] are $6{n^{2}} + O(n)$ and $8{n^{2}} - 4n$, respectively. But, the two multipliers also require $O({n^{2}})$ quantum measurements. We compare the proposed multiplier against recent works without quantum measurements [23, 35, 36]. Two multipliers are proposed in [36], but the second multiplier has better performance indexes than the first multiplier. Therefore, we only compare the proposed multiplier with the second multiplier in [36]. The results are presented in Table 6 and Table 7, which illustrate that the proposed multiplier is superior to the others for the five performance indexes. For instance, the CNOT-count of the proposed 32-bit multiplier achieves improvement ratios of 50.20 percent, 54.35 percent, and 26.96 percent compared to the works presented in [23, 35, 36], respectively. The caveat is that the proposed multiplier can only realize the special multiplication ab with $a \ne 0$. The other three multipliers do not have this limitation. The proposed multiplier based on LI gates has another advantage: it can be easily used to design dividers.

Table 6 Comparisons of multipliers for $n \ge 3$

Table 7 Comparisons of multipliers by increasing n from 4 to 32. C-count and C-depth denotes CNOT-count and CNOT-depth, respectively

Note: Performance indexes of the multiplier in [36] are miscalculated. We recalculate them as follows. The n-bit multiplier consists of an SM module, $n-1$ modular adder-subtractors (($n+1$)-bit), an ($n+1$)-bit modular adder, and an Aswap module. Performance indexes of the modular adder and modular adder-subtractor in [36] have been listed in Table 4. The SM module has $20n-9$ T-counts, $5n-1$ T-depth, $33n-23$ CNOT-counts, and $21n-21$ CNOT-depths. The Aswap module has 4n T-counts, 2 T-depths, 6n CNOT-count, and 5 CNOT-depths. Performance indexes of the n-bit multiplier are calculated by

$$ \textstyle\begin{cases} {\text{T-count: }}20n - 9 + [8(n + 1) - 9](n - 2) + 8(n + 1) \\ \qquad{}- 9 + 4n= 8{n^{2}} + 15n - 8, \\ {\text{T-depth: }}5n - 1 + [2(n + 1) - 1](n - 2) + 2(n + 1) +1 \\ \quad= 2{n^{2}} + 4n, \\ {\text{CNOT-count: }}33n - 23 + [15(n + 1) - 23](n - 2) \\ \qquad{}+ 13(n + 1) - 21 + 6n = 15{n^{2}} + 14n - 15, \\ {\text{CNOT-depth: }}21n - 21 + [8(n + 1) - 10](n - 2) \\ \qquad{}+ 8(n + 1) - 12 + 5= 8{n^{2}} + 11n - 16. \end{cases} $$

6.2.3 Performance comparisons of dividers

We compare the proposed divider against recent works [36, 38]. Thapliyal et al. design restoring and non-restoring dividers [38]. The non-restoring divider has a smaller T-count and T-depth than the restoring divider, so we only compare the proposed divider with the non-restoring divider. The results in Table 8 and Table 9 illustrate that the proposed divider is superior to the others in terms of T-count, T-depth, CNOT-count, and CNOT-depth. For instance, the proposed 32-bit divider achieves improvement ratios of 40.41 percent, 31.64 percent, 45.27 percent, and 65.93 percent in terms of T-count, T-depth, CNOT-count, and CNOT-depth compared to the work presented in [36]. Meanwhile, the proposed 32-bit divider reduces T-count by 45.54 percent, T-depth by 67.62 percent, CNOT-count by 47.36 percent, and CNOT-count by 68.85 percent when compared with the work in [38]. The n-bit division requires at least 3n qubits to store the quotient, remainder, and operand; thus, the proposed divider has the minimum circuit width 3n for the n-bit division keeping an operand unchanged.

Table 8 Comparisons of dividers for $n \ge 3$

Table 9 Comparisons of dividers by increasing n from 4 to 32. C-count and C-depth denotes CNOT-count and CNOT-depth, respectively

Note: Thapliyal et al. designed a non-restoring divider to realize the positive 2’s complement division [38]. An n-bit positive integer can be changed into the complement number by adding a binary 0 before the high bit. Therefore, a complement operand of the n-bit positive integer division requires $m=n+1$ bits. The n-bit divider consists of an m-bit modular subtractor named Subtraction, $(m-1)$ m-bit modular adder-subtractor named Ctrl-AddSub, and an $(m-1)$-bit controlled modular adder named Ctrl-AddNOP [38]. Performance indexes of the three modules can be found in Table 4. Then, performance indexes of the n-bit divider are calculated by

$$ \textstyle\begin{cases} {\text{T-count: }} \\ 14m - 14 + (14m-14)(m-1)+ 21(m-1)-14 \\ \quad = 14{m^{2}}+7m-35 \\ \quad =14{n^{2}}+35n-14, \\ {\text{T-depth: }} \\ 6m-6+(6m-6)(m-1) + 9(m-1)-6 \\ \quad= 6{m^{2}}+3m-15 \\ \quad =6{n^{2}}+15n-6, \\ {\text{CNOT-count: }} \\ 17m-18 + (20m-18)(m-1)+25(m-1)-20 \\ \quad = 20{m^{2}}+4m-45 \\ \quad =20{n^{2}}+44n-21, \\ {\text{CNOT-depth: }} \\ 13m-12 + (13m-10)(m-1)+20(m-1)-14 \\ \quad = 13{m^{2}}+10m-36 \\ \quad =13{n^{2}}+36n-13, \\ {\text{width: }} 3m-1= n+2, \end{cases} $$

with $m=n+1$.

7 Conclusions and future works

In this paper, we have proposed a special multiplier and a divider based on LI and approximate Toffoli gates. We designed circuits of basic arithmetic operations used in the proposed multiplier and divider, such as the modular adder, modular adder-subtractor, controlled modular adder, special modular adder, special modular adder-subtractor, and their inverses. These basic arithmetic operations based on LI gates have the advantage that their inverse can be realized by inverting the circuit order of the corresponding arithmetic operations. We have proposed new rules of LI gates to design Clifford + T circuits of the proposed multiplier and divider, optimizing T-count, T-depth, CNOT-count, and CNOT-depth. Clifford + T circuits of the proposed multiplier and divider are superior to existing multiplier and dividers in terms of T-count, T-depth, CNOT-count, and CNOT-depth. Furthermore, circuit widths of the proposed n-bit multiplier and divider are 3n. That is, our multiplier and divider have reached the minimum width of multipliers and dividers, keeping an operand unchanged. As a future work, it will be interesting to apply the proposed multiplier and divider in quantum image processing, such as quantum bilinear interpolation algorithm.